Many applications in modern electronics require that continuous-time signals be converted to discrete signals for processing using digital computers and signal processors. Typically, this transformation is made using a conventional analog-to-digital converter (ADC). However, the present inventor has discovered that each of the presently existing approaches exhibits shortcomings that limit overall performance at very high sample rates.
Due to parallel processing and other innovations, the digital information processing bandwidth of computers and signal processors has advanced beyond the capabilities of state-of-the art ADCs. Converters with higher instantaneous bandwidth are desirable in certain circumstances. However, existing solutions are limited by instantaneous bandwidth (effective sample rate), effective conversion resolution (number of effective bits), or both.
The resolution of an ADC is a measure of the precision with which a continuous-time continuously variable signal can be transformed into a quantized signal, and typically is specified in units of effective bits. When a continuous-time continuously variable signal is converted into a discrete-time discretely variable signal through sampling and quantization, the quality of the signal degrades because the conversion process introduces quantization, or rounding, noise. High-resolution converters introduce less quantization noise because they transform continuously variable signals into discrete signals using a rounding operation with finer granularity. Instantaneous conversion bandwidth is limited by the Nyquist criterion to a theoretical maximum of one-half the converter sample rate (the Nyquist limit). High-resolution conversion (>10 bits) conventionally has been limited to instantaneous bandwidths of about a few gigahertz (GHz) or less.
Converters that quantize signals at a sample rate (fS) that is at or slightly above a frequency equal to twice the signal bandwidth (fB) with several or many bits of resolution are conventionally known as Nyquist-rate converters. Prior-art Nyquist-rate converter architectures include conventional flash and conventional pipeline analog-to-digital converters (ADCs). Conventional flash converters potentially can achieve very high instantaneous bandwidths. However, the resolution of flash converters can be limited by practical implementation impairments that introduce quantization errors, such as clock jitter, thermal noise, and rounding/gain inaccuracies caused by component tolerances. Although flash converters potentially could realize up to 9 bits of resolution at instantaneous information bandwidths greater than 10 GHz, this potential has been unrealized in commercial offerings. Conventional pipeline converters generally have better precision than commercial flash converters, because they employ complex calibration schemes to reduce the quantization errors caused by these practical implementation impairments. However, pipeline converters typically can provide less than about 1 GHz of instantaneous bandwidth.
Another conventional approach that attempts to reduce quantization noise and errors uses an oversampling technique. Oversampling converters sample and digitize continuous-time, continuously variable signals at a rate much higher than twice the analog signal's bandwidth (i.e., fS>>fB). Due to operation at very high sample rates, the raw high-speed converters used in oversampling approaches ordinarily are capable of only low-resolution conversion, often only a single bit. Conventional oversampling converters realize high resolution by using a noise-shaping operation that ideally attenuates quantization noise and errors in the signal bandwidth, without also attenuating the signal itself. Through quantization noise shaping and subsequent filtering (digital signal reconstruction), oversampling converters transform a high-rate, low-resolution output into a low-rate, high-resolution output.
FIGS. 1A-C illustrate block diagrams of conventional, lowpass oversampling converters. A typical conventional oversampling converter uses a delta-sigma modulator (DSM) 7A-C to shape or color quantization noise. As the name implies, a delta-sigma modulator 7A-C shapes the noise that will be introduced by quantizer 10 by performing a difference operation 8 (i.e., delta) and an integration operation 13A-C (i.e., sigma), e.g.,
      H    ⁡          (      z      )        =                    z                  -          1                            1        -                  z                      -            1                                .  Generally speaking, the delta-sigma modulator processes the signal with one transfer function (STF) and the quantization noise with a different transfer function (NTF). Conventional transfer functions are of the form STF(z)=1 and NTF(z)=(1−z−1)P, where z−1 represents a unit delay equal to TS=1/fS, and P is called the order of the modulator or noise-shaping response. The noise transfer function has a frequency response given by NTF(e−sT)=(1−e−sTS)P. The STF frequency response 30 and NTF frequency response 32 for P=1 are shown in FIG. 2.
There exist various types of conventional delta-sigma modulators that produce equivalent signal and noise transfer functions. A delta-sigma modulator that employs an auxiliary sample- and hold operation, either explicitly as in sample-and-hold circuit 6 in filters 5A&C shown in FIGS. 1A&C, respectively, or implicitly using switched-capacitor circuits, for example, is commonly referred to as a discrete-time, delta-sigma modulator (DT DSM). A delta-sigma modulator that does not employ a sample-and-hold operation, such as filter 7B shown in FIG. 1B, is commonly referred to as a continuous-time, delta-sigma modulator (CT DSM). Discrete-time modulators have been the preferred method in conventional converters because DT DSMs are more reliable in terms of stable (i.e., insensitivity to timing variations) and predictable (i.e., linearity) performance. See Ortmans and Gerfers, “Continuous-Time Sigma-Delta A/D Conversion: Fundamentals, Performance Limits and Robust Implementations”, Springer Berlin Heidelberg 2006. The converters 5A&B, shown in FIGS. 1A&B, respectively, employ delta-sigma modulators with filtering 13A&B in the feed-forward path from the output of the modulator adder 8 to the input of the quantizer 10, in an arrangement known as an interpolative structure. An alternative is the error-feedback structure of converter 5C shown in FIG. 1C, which has no feed-forward filtering. It does not appear that the conventional error-feedback modulator has any performance or implementation advantage relative to the interpolative (feed-forward) structure, which is the preferred method in conventional continuous-time converters.
As illustrated in FIGS. 1A-C, conventional oversampling converters employ a comb or sinc filter 12 for quantization noise filtering and signal reconstruction. Conventional oversampling converters with first-order noise shaping realize the comb filter 12 in three steps: second-order integration 12A, e.g., with a transfer function of
  1            (              1        -                  z                      -            1                              )        2  at the converter sample rate (fS or fCLK), followed by downsampling 12B at the converter oversampling ratio (N), followed by second-order differentiation 12C, e.g., with a transfer function of(1−z−1)2 at the converter output rate. A generalized comb filter transfer function of
            F      ⁡              (        z        )              =                  (                              1            -                          z                                                -                  2                                ⁢                N                                                          1            -                          z                              -                1                                                    )                    P        +        1              ,where P is the order of the modulator, produces local minima at multiples of the output data rate, and conventionally has been considered optimal for oversampling converters. Thus, in the specific example given above, it is assumed that a modulator with first-order response is used.
The delta-sigma converters 5A-C illustrated in FIGS. 1A-C are conventionally known as lowpass, delta-sigma converters. A variation on the conventional lowpass converter, employs bandpass delta-sigma modulators to allow conversion of narrowband signals that are centered at frequencies above zero. Exemplary bandpass oversampling converters 40A&B, illustrated in FIGS. 3A&B, respectively, include a bandpass delta-sigma modulator 42A or 42B, respectively, that provides, as shown in FIG. 4, a signal response 70 and a quantization-noise response 71 with a minimum 72 at the center of the converter Nyquist bandwidth (i.e., fS/4). After single-bit high-speed quantization/sampling 10 (or, with respect to converter 40A shown in FIG. 3A, just quantization, sampling having been performed in sample-and-hold circuit 6), quantization noise filtering 43, similar to that performed in the standard conventional lowpass oversampling converter (e.g., any of converters 5A-C), is performed, followed by downsampling 44.
Bandpass delta-sigma modulators are similar to the more-common lowpass variety in several respects: The conventional bandpass delta-sigma modulator has both discrete-time (converter 40A shown in FIG. 3A) and continuous-time (converter 40B shown in FIG. 3B) forms. Like the lowpass version, the bandpass delta-sigma modulator 42A&B shapes noise from quantizer 10 by performing a difference operation 8 (i.e., delta) and an integration operation 13A&B (i.e., sigma), respectively, where
      H    ⁡          (      z      )        =                              z                      -            1                                    1          -                      z                          -              1                                          ⁢                          ⁢      and      ⁢                          ⁢              H        ⁡                  (          s          )                      =                  As                              s            2                    +                      ω            2                              .      Also, the bandpass modulator processes the signal with one transfer function (STF) and the quantization noise with a different transfer function (NTF). Conventional transfer functions are of the form STF(z)=1 and NTF(z)=(1+α·z−1+z−2)P, where z−1 represents a unit delay equal to TS and P is the modulator noise-shaping order.
As shown above, the noise transfer function (NTF) of a real bandpass delta-sigma modulator is at minimum a second-order response. The modulator coefficient, α, determines the location of a spectral notch (fnotch), or null, in the noise transfer function frequency response according to NTF(e−sT)=(1−α·e−sTS+z−2sTS). The frequency of fnotch typically is set to coincide with the center of the input signal bandwidth. Quantization noise minima are placed at arbitrary locations in the converter band by allowing the modulator coefficient, α, to vary continuously over a range of −2 to +2, such that α=−2·cos(2·π·fnotch·TS). A bandpass delta-sigma modulator is equivalent to a second-order, lowpass delta-sigma modulator when α=−2 becauseNTF(z)=(1−2·z−1+z−2)=(1−z−1)2.
Conventional oversampling converters can offer very high resolution, but the noise filtering and signal reconstruction process generally limits the utility of oversampling converters to applications requiring only low instantaneous bandwidth. To improve the instantaneous bandwidth of oversampling converters, multiple oversampling converters can be operated in parallel using the time-interleaving (time-slicing) and/or frequency-interleaving (frequency-slicing) techniques developed originally for Nyquist converters (i.e., flash, pipeline, etc.). In time-interleaving, a high-speed sample clock is decomposed into lower-speed sample clocks at different phases. Each converter in the time-interleaved array is clocked with a different clock phase, such that the conversion operation is distributed in time across multiple converters. While converter #1 is processing the first sample, converter #2 is processing the next sample, and so on.
In frequency interleaving, the total bandwidth of the continuous-time signal is divided into multiple, smaller sub-bands. According to one representative implementation of a frequency interleaving ADC 70A, shown in FIG. 5A, the individual bands are separated out and down-converted to baseband. More specifically, the input signal 71 is provided to a set of multipliers 72 together with the band's central frequencies 74A-76A. The resulting baseband signals are then provided to lowpass, anti-aliasing filters 78. Each such filtered baseband signal is then digitized 80A, digitally upconverted (or upsampled) 82A using digitized sinusoids 83A-C and then bandpass filtered 84A-86A in order to restore it to its previous frequency band. Finally, the individual bands are recombined in one or more adders 88. Each converter 80A in the interleaved array is able to operate at a submultiple of the overall sample rate, due to the reduced signal bandwidth in each of the subdivided, down-converted bands.
The conventional parallel delta-sigma analog-to-digital converter (ΠΔΣADC) 70B, shown in FIG. 5B, is similar in design and operation to the conventional frequency-interleaved converter 70A shown in FIG. 5A, except that oversampling converters 80B are used in place of multi-bit digitizers 80A and anti-aliasing filters 78. See I. Galton and H. Jensen, “Delta Sigma Modulator Based A/D Conversion without Oversampling”, IEEE Transactions on Circuits and Systems, Vol. 42, 1995 and I. Galton and T Jensen, “Oversampling Parallel Delta-Sigma Modulator A/D Conversion”, IEEE Transactions on Circuits and Systems, Vol. 43, 1996). As shown in FIG. 5B, the primary advantage of the prior-art ΠΔΣ converter 70B is that the oversampling operation of the delta-sigma modulators 89 eliminates the need for the anti-aliasing function provided by the analog filter bank. The conventional ΠΔΣADC generally employs discrete-time, lowpass delta-sigma modulators 89 and uses continuous-time Hadamard sequences (vi(t)) 74B-76B and discrete-time Hadamard sequences (ui[n]) 89A-C, instead of sinusoidal waveforms, to reduce the circuit complexity associated with the downconversion 72B and upconversion 82B operations. In some instances, bandpass delta-sigma modulators are used to eliminate the need for analog downconversion completely, in a process sometimes called Direct Multi-Band Delta-Sigma Conversion (MBΔΣ). See Aziz, P., “Multi-band Oversampled Noise Shaping Analog to Digital Conversion” (PhD Thesis), University of Pennsylvania, 1996 and A. Beydoun and P. Benabes, “Bandpass/Wideband ADC Architecture Using Parallel Delta Sigma Modulators”, 14th European Signal Processing Conference, 2006. In addition to multi-band delta-sigma modulation, conventional frequency-interleaved, oversampling converters (i.e., ΠΔΣADC and MBΔΣ) employ conventional combP+1 (ΠΔΣADC) filters or conventional filter bank (MBΔΣ) signal reconstruction schemes.
The present inventor has discovered that conventional ΠΔΣ converters, as shown in FIG. 5B, and conventional MBΔΣ converters have several disadvantages that limit their utility in applications requiring very high instantaneous bandwidth and high resolution. These disadvantages, which are discussed in greater detail in the Description of the Preferred Embodiment(s) section, include: (1) use of delta-sigma modulation (Galton, Aziz, and Beydoun) impairs high-frequency operation because the sample-and-hold operation limits the performance of DT DSMs and non-ideal circuit behavior can degrade the noise-shaping response and stability of CT DSMs; (2) use of comb filters for signal reconstruction in ΠΔΣ converters (Galton) introduces amplitude and phase distortion that is not completely mitigated by the output equalizer (i.e., equalizer 90 having transfer function D(z) in FIG. 5B); (3) use of Hadamard sequences for downconversion and upconversion in ΠΔΣ converters introduces conversion errors related to signal-level mismatches and spectral images; (4) use of conventional filter-bank technology (as in Aziz) or Hann window filters (as in Beydoun) for signal reconstruction in MBΔΣ converters limits the practical number of parallel processing branches/channels due to signal-processing complexities (i.e., number of multiply/accumulates), particularly for high-frequency, multi-rate (i.e., polyphase) filter topologies; and (5) absence of feedback from the signal-reconstruction filter outputs to the DSM, means that DSM component tolerances can degrade converter performance by creating mismatches between the notch frequency (fnotch) in the NTF and the center frequency of the narrowband reconstruction notch, filter response. Possibly due to these disadvantages, the instantaneous bandwidth and resolution performance of conventional ΠΔΣ and MBΔΣ converters have not been able to surpass that of conventional pipeline converters.
In addition to ΠΔΣ and MBΔΣ, parallel arrangements of delta-sigma modulators are the subject of several United States patents, such as U.S. Pat. Nos. 7,289,054, 6,873,280, and 6,683,550. However, these patents generally fail to adequately address the primary issues associated with the high-resolution, high-sample-rate conversion of continuous-time signals to discrete-time signals. One technique, described in U.S. Pat. No. 7,289,054, uses digitization of noise-shaping-filter residues for increasing converter precision, rather than using reconstruction filter banks for quantization noise reduction. Another technique, described in U.S. Pat. No. 6,873,280, addresses conversion of digital (discrete-time, discretely variable) signals to other forms, rather than the conversion of analog (continuous-time, continuously variable) signals to digital signals. A third technique, described in U.S. Pat. No. 6,683,550, employs multi-bit, first-order modulators which are not suitable for high-precision, bandpass oversampling applications since these application require modulators that are at least second order.